For years, the story of AI hardware was about raw compute: faster processors, more of them, crunching bigger models. The bottleneck has moved.
According to EE Times, French research institute CEA-Leti is pushing a roadmap built around 3D stacking, chiplets, and cooler power delivery — a response to what the industry calls the "memory wall." The idea behind that term is simple enough: a processor can only work as fast as data reaches it, and moving data in and out of memory has become the limiting factor, along with the electricity and heat that movement generates.
EE Times frames the shift bluntly — packaging is turning into architecture. Historically, packaging was the unglamorous final step of wrapping a finished chip. Now how chips are stacked vertically, split into smaller specialized pieces called chiplets, and wired together is itself a core design decision, on par with the circuitry inside.
The same pressure is showing up in policy. Electronics360, reported via Google News, says the CHIPS Act is targeting AI's compute bottleneck through memory, optics, and packaging — the same three areas, suggesting that public funding is tracking where engineers say the constraint actually sits rather than chasing transistor counts alone.
Neither source claims the wall has been broken. Both describe an industry redirecting its effort.
Why it matters: if the limits on AI are increasingly about memory bandwidth and power rather than processor speed, then the cost, energy footprint, and pace of AI progress will be decided as much by how chips are assembled and cooled as by how small their transistors get.