Intel's advanced chip-packaging technology, called EMIB, is winning attention from chipmakers frustrated by supply constraints on a rival technology from Taiwan's TSMC, according to Tom's Hardware.
Modern AI chips are often built by stitching multiple pieces of silicon together inside a single package. TSMC's method for doing this, known as CoWoS, has become a chokepoint as demand for AI hardware surges. That has designers hunting for alternatives.
Tom's Hardware reports that Google has reportedly chosen Intel's EMIB-T over TSMC's CoWoS-L for its next-generation, 9th-generation TPU, an AI accelerator codenamed Humufish. Tom's Hardware frames the decision as evidence that Intel offers an attractive way to sidestep TSMC's capacity limits, while noting the choice is so far based on reports and raising the open question of whether other designers will follow Google's lead.
The packaging story arrives as Intel pushes forward on another front. Tech Times reports that Intel has put the first High-NA EUV logic chip into mass production, describing the company as leading the foundry race on that milestone. High-NA EUV is a cutting-edge chipmaking technique built on machines from Dutch supplier ASML. According to simplywall.st, ASML has reached a High-NA milestone of its own as Intel's production begins.
Together, the reports point to Intel positioning itself as a credible alternative to TSMC across two areas where TSMC has dominated: the leading-edge manufacturing that prints tiny transistors, and the packaging that assembles finished chips.
Why it matters: if a marquee customer like Google is genuinely shifting packaging work to Intel, it signals that TSMC's grip on the AI-chip supply chain is loosening, potentially reshaping who builds the hardware powering the AI boom.