The way the chips that power artificial intelligence are physically assembled is changing, and the shift could matter as much as the silicon itself.
For years, advanced chip packaging has been a largely flat affair. As SemiWiki explains, engineers placed "chiplets" side by side and wired them together through layers called interposers, bridges, redistribution layers, and substrates, using short-reach electrical links. According to SemiWiki, this planar approach still underpins today's GPUs, high-bandwidth memory (HBM), chiplet designs, and so-called 2.5D integration.
But SemiWiki frames a new direction for the AI era: a "tower-like" heterogeneous packaging architecture. Rather than spreading components out sideways, the idea points toward building upward, stacking different kinds of chips into a more vertical structure.
That evolution runs alongside a separate debate over how to make AI processors physically bigger. According to Reuters reporting carried by MSN, TSMC, the world's leading contract chipmaker, says panel-level packaging will not replace its established CoWoS technology anytime soon for the largest future AI processors. A newer approach known as CoPoS may eventually enable larger chips, TSMC indicates, but the company maintains that CoWoS remains the better option for now.
The common thread is that the limits of flat, single-chip designs are pushing the industry toward new geometries, whether that means stacking chips into towers or rethinking the panels they sit on.
Why it matters: As AI models grow, the bottleneck is increasingly not just how fast a chip computes but how its parts are packaged and connected, making these packaging choices a quiet but decisive factor in the pace of AI progress.