Chip / Hardware

CoWoS

10 briefings tracked

CoWoS (Chip on Wafer on Substrate) is an advanced chip-packaging technology developed by TSMC that integrates multiple semiconductor dies—including compute chips and high-bandwidth memory—onto a shared silicon interposer, enabling far denser interconnects than traditional packaging allows.

As AI models have grown in scale, the bandwidth and proximity between processor and memory have become critical performance bottlenecks. CoWoS addresses this by placing components such as GPU dies and HBM stacks side by side on a single substrate, dramatically increasing the speed at which data moves between them. TSMC's leadership in this area has made it an essential supplier to major AI chip designers.

Chip packaging has emerged as a new competitive front in the AI hardware race. TSMC maintains that CoWoS outperforms emerging panel-level packaging alternatives for the largest AI processors, yet the company is already accelerating a next-generation successor technology to meet the demands of increasingly powerful AI chips. This evolution reflects a broader industry recognition that packaging innovation is now as strategically important as advances in transistor design itself.

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